1. Field of the Invention
The present invention relates to a MOS solid-state imaging device for use in a digital camera or the like, and a method for driving the same.
2. Description of the Related Art
In recent years, as the function, miniaturization level and the like of imaging elements are improved, solid-state imaging devices (imaging chips) including the imaging element are employed within an increasing range of applications. For example, while a solid-state imaging device having a miniaturized imaging element is incorporated into a mobile telephone or the like, a solid-state imaging device adapted to improve image quality is used in a high-grade digital camera or the like, such as a single-lens reflex camera or the like. Solid-state imaging devices used in any products have basic common features, and each comprise a pixel array of a plurality of cells which receive external light.
FIGS. 27A to 27C are plan views illustrating cells in a MOS solid-state imaging device according to a first conventional example. FIG. 27A illustrates an impurity diffusion layer and a polysilicon wiring layer formed on a semiconductor substrate, and contacts connecting between the semiconductor substrate or the polysilicon wiring layer and wires of a first metal wiring layer. FIG. 27B is a plan view illustrating wires formed in the first metal wiring layer in addition to the configuration of 27A. FIG. 27C is a plan view illustrating wires formed in a second metal wiring layer in addition to the configuration of FIG. 27B. FIG. 28 is a diagram illustrating a cross-section of the solid-state imaging device of the first conventional example, taken along line XXVIII-XXVIII of FIG. 27C.
As illustrated in FIGS. 27A to 27C, each conventional cell comprises: a photodiode 2501 which accumulates an amount of electric charges corresponding to the intensity of received light; a floating diffusion (hereinafter abbreviated as “FD”) 2530 to which electric charges accumulated by the photodiode 2501 are transferred; a transfer transistor 2502 which is controlled by the potential of a transfer gate wire 2508 to control transfer of electric charges from the photodiode 2501 to the FD 2530; a reset transistor 2704 which is controlled by a reset gate wire 2507 to initialize the potential of the FD 2530; an amplifying transistor 2703 which has a gate electrode connected to the FD 2530, a drain connected to a power supply line 2505, and a source to a vertical signal line 2506 to form a source follower; an FD wire 2535 which connects a gate wire 2509 of the amplifying transistor 2703 and the FD 2530; and a wire 2513. In the example of FIGS. 27A to 27C, the power supply line 2505 and the vertical signal line 2506 are formed in the first metal wiring layer, and the wire 2513 is formed in the second metal wiring layer. The FD wire 2535 is formed in the first metal wiring layer, and the gate wire 2509 is formed in the polysilicon wiring layer. In the pixel array, the cells and the photodiodes 2501 are arranged in a matrix (array). The FD wire 2535 and the gate wire 2509 are formed in each cell. In FIGS. 27A to 27C, a gate wire in a cell adjacent to the cell in which the gate wire 2509 is provided is indicated as a gate wire 2509″. Also, a vertical signal line adjacent to the vertical signal line 2506 is indicated as a vertical signal line 2506″ for the sake of convenience.
FIG. 29 is a diagram illustrating an outline of the pixel array of the conventional solid-state imaging device. As illustrated in FIG. 29, in the conventional solid-state imaging device, a plurality of cells 2600 are arranged in a matrix to form a pixel array. A substrate contact wire 2540 is provided for each column of cells 2600, and is shared by a plurality of cells 2601 for substrate contact provided in the column. In the pixel array, a substrate contact cell 2601 is provided every a predetermined number of pixels.
FIG. 30 is a schematic diagram illustrating another exemplary pixel array of a conventional solid-state imaging device. A color filter is provided on each pixel so that the pixel recognizes any of G (green), R (red), and B (blue). In this example, the pixel array is composed of units each of which includes 2×2 pixels which recognize G, R and B. This color arrangement is generally called a Bayer array.
An operation of the thus-configured solid-state imaging device will be described.
Initially, when a vertical shift register (not shown) outputs a reset pulse signal, the reset transistor 2704 (see FIGS. 27A to 27C) is operated so that the FD 2530 is initialized to the potential of the power supply line 2505. Next, when light impinges on the photodiode 2501, electric charges are accumulated in the photodiode 2501. Thereafter, electric charges accumulated in the photodiode 2501 are transferred to the FD 2530 via the transfer transistor 2502 selected by the vertical shift register. The potential of the FD 2530 is changed by the transferred electric charges. When the potential of the FD 2530 is changed, the potential of the vertical signal line 2506 is changed via the amplifying transistor 2703. The change in the potential of the vertical signal line 2506 is transmitted through a noise suppressing circuit (not shown), and is then output to a horizontal signal line which is controlled by a transistor in a column selected by a horizontal shift register.
FIG. 31 is a circuit diagram illustrating a cell of a general MOS solid-state imaging device.
As illustrated in FIG. 31, a cell 2901 comprises: a photodiode 2902 which accumulates an amount of electric charges corresponding to the intensity of received light; a floating diffusion (hereinafter abbreviated as “FD”) 2903 to which electric charges accumulated by the photodiode 2902 are transferred; a transfer transistor 2911 which is controlled by a transfer gate wire 2904 to control transfer of electric charges from the photodiode 2902 to the FD 2903; a capacitance including a wire capacitance and the like connected to the FD 2903; a reset transistor 2912 which is controlled by a reset gate wire 2905 to initialize the potential of the FD 2903; and an amplifying transistor 2908 which has a gate electrode connected to the FD 2903, a drain connected to a power supply line 2906, and a source connected to a vertical signal line 2907 to form a source follower. In FIG. 31, the FD 2903 is illustrated as a node between the drain of the transfer transistor 2911 and the gate electrode of the amplifying transistor 2908. The transfer transistor 2911, the reset transistor 2912, and the FD 2903 function as a read control circuit 2909.
FIGS. 32A to 32C are plan views illustrating an exemplary layout of a conventional pixel array (second conventional example). FIG. 32A illustrates a polysilicon wiring layer, and contacts connecting a diffusion layer or polysilicon wires formed on a semiconductor substrate and a first metal wiring layer, in the pixel array. FIG. 32B illustrates wires formed in the first metal wiring layer or below, and each contact. FIG. 32C illustrates wires formed in a second metal wiring layer or below, and each contact. In FIGS. 32A to 32C, each portion surrounded by a dashed line is a cell 2901.
As illustrated in FIGS. 32A to 32C, the gate electrode of the transfer transistor 2911 and the gate electrode of the amplifying transistor 2908 are formed in the polysilicon wiring layer, and the first metal wire 2907 and a second metal wire 2920 are each formed in the first metal wiring layer. The third metal wire 2906 is formed in the second metal wiring layer.
FIG. 33 is a diagram illustrating an exemplary conventional layout of a pixel array 3001 in which a plurality of cells are arranged (third conventional example). In the conventional pixel array 3001, a light-shielded pixel region 3202 is provided around an effective pixel region 3201. The light-shielded pixel region 3202 is provided so as to detect a black color which may be used as a reference. In the light-shielded pixel region 3202, a metal wire is provided over an entire surface of the cell so that light is blocked from entering the photodiode.
FIG. 34 is a diagram illustrating an exemplary cross-section in the effective pixel region of the pixel array of the conventional solid-state imaging device.
In order to improve the oblique incident light characteristics of photodiodes 3301, 3302 and 3303, wires 3314, 3315 and 3316 are shifted from positions 3307, 3308 and 3309 to positions 3304, 3305 and 3306, i.e., toward a center line of the pixel array, by amounts which increase with an increase in the distances of the wires from the center line. Shifting the position of a wire toward the center line is referred to as “shrink”.